1a.
This invention relates to a so-called frame-thinning type half-tone representation system, and more particularly to a half-tone representation system which is suitable for use with a multi-color liquid crystal display apparatus.
2b.
Japanese Laid-open Patent Application No. 58-57192 shows a half-tone representation system for a monochrone liquid crystal display apparatus with high-speed blinking of picture elements or pixels.
This prior art half-tone representation system is described below with reference to FIGS. 2, 3, 4 and 5.
FIG. 2 shows a block diagram of such a prior art half-tone representation system. In the drawing, an oscillator for generating a 8-dot reference clock or character clock signal 2 is indicated at 1; display address signal generator responsive to reference clock signal 2 for cyclically generating display addresses 4 for a single frame is indicated at 3; and display memories for storing 8-bit display data 61-64 are indicated at 51-54. Pieces of display information are stored in each of the memories 51-54 in one-to-one correspondence relation, and 8-bit display data 61-64 retrieved from each of memories 51-54 are in one-to-one correspondence relation in terms of bit unit. When all display data 61-64 are "LOW", "display OFF" is indicated; when all display data 61-64 are "HIGH", "display ON" is indicated; and otherwise, half-tone representation is indicated. A timing signal generator is indicated at 9; a frame signal is indicated at 10; a line signal is indicated at 11; a data shift signal is indicated at 12; and an AC drive signal is indicated at 13. The timing signal generator 9 generates the frame signal 10, the line signal 11, the data shift signal 12 and the AC drive signal 13 in response to the character clock signal 2. A half-tone controlling circuit is indicated at 14; a divide-by-three frame counter which uses the frame signal 10 as a clock signal for cyclically generating "0", "1" and "2", is indicated at 15; a frame count outputted by frame counter 15 is indicated at 16; a half-tone signal generator is indicated at 24; and a half-tone signal is indicated at 25. The half-tone signal generator 24 outputs a half-tone signal of "HIGH" when frame count 16 is, " 0", and a half-tone signal of "LOW" when frame count 16 is "1" or "2". A display controlling circuit is indicated at 21 and 8-bit liquid crystal display data is indicated at 22. The display controlling circuit 21 functions to output as liquid crystal display data, a binary signal "HIGH" for normal representation or "display ON"; a binary signal "LOW" for "display OFF"; and is also controlled by half-tone signal 25 for half-tone representation. Liquid crystal display panel 231 composed of "m" dots x "n" lines is responsive to the liquid crystal display data 22 for providing visual representation of the data.
In FIG. 2, the display address generator circuit 3 functions to output addresses 4 to the display memories 51-54, thereby retrieving display information from memories 51-54. Each of the retrieved display information is of 8 bits, and is directed as display data to the display controlling circuit 21. The display controlling circuit 21 is responsive to the binary condition of each bit of display data 61-64 for outputting 8-bit liquid crystal display signal 22 to the liquid crystal display panel 231, specifically outputting display data signal of "HIGH" for normal display or "display ON"; display data signal of "LOW" for "display OFF"; of half-tone data which is "HIGH" in each one out of three frames in response to signal 25. The display address generator circuit 3 sequentially supplies display data 8 bits at a time to the liquid crystal panel 231 so as to sequentially provide display data of a frame. The liquid crystal display panel 231 functions to sequentially latch the liquid crystal display data 22 with data shift clock 12. After latching sufficient liquid crystal display data 22 to fill a full line of "m" dots, visual representation may be provided by means of line clock pulse 11, which pulse appears once for each line. This will be repeated "n" times to provide visual representation in a single frame. The beginning of each frame is indicated by the frame signal 10, and the liquid crystal display panel 231 is responsive to each appearance of "HIGH" frame signal 10 for beginning visual representation with the top line.
The above procedure is repeated to provide visual representation of all information stored in the memories 51-54.
FIG. 3 shows how liquid crystal panel 231 provides normal and half-tone representation of the liquid crystal display data 22 in the "0"th, 1st and 2nd frames.
Now, assume that information representing the letter "A" is stored in each of the display memories 51-54, and that information representing the letter "B" is stored only in the display memory 51. Then, the display controlling circuit 21 functions to output a binary signal of "HIGH" in each frame for the letter "A" and a half-tone signal 25 for the letter "B". Specifically, since frame counter 15 provides "0" in the "0"th frame, the half-tone signal 25 is "HIGH", allowing liquid crystal display panel 231 to provide visual representation of both letters "A" and "B" in the "0"th frame. The half-tone signal 25 is "LOW" in the 1st and 2nd frames, and then no visual representation of the letter "B" is caused in liquid crystal display panel 231 in these frames. Thus, the letter "B" will appear in only one frame out of three frames, and as a result the effective voltage applied to the liquid crystal panel 231 lowers compared with that for the letter "A". Thus, half-tone representation of the letter "B" is realized.
FIG. 4 shows a block diagram of a conventional liquid crystal display apparatus employing a multi-color liquid crystal display panel. Color liquid crystal display panel is indicated at 23; and red (R), green (G) and blue (B) liquid crystal display data are indicated at 221, 222 and 223. Same components as appear in FIG. 2 are indicated at same reference numerals in FIG. 4.
Display controlling circuit 21 is responsive to display data 61-64 for providing R-liquid crystal display data 221, G-liquid crystal display data 222 and B-liquid crystal display data 223, each of which will be "HIGH" for normal display or "display ON", "LOW" for "display OFF", and will be controlled by the half-tone signal 25 for half-tone representation. Color liquid crystal display panel 23 includes dots each made up by a R-pixel, G-pixel and B-pixel. The R-pixel provides a visual representation of R-liquid crystal display data 221; the G-pixel provides visual representation of G-liquid crystal display data 222; and the B-pixel provides a visual representation of B-liquid crystal display data 223. The operation of the system of FIG. 4 is essentially the same as that of FIG. 2, except for the following:
FIG. 5 show how color liquid crystal panel 23 provides half-tone representation of R-, G- and B-liquid crystal display data 221-223 in the "0"th frame, the 1st frame and the 2nd frame. In the drawing, visual half-tone representation of the letter "A" is provided for every R-, G- and B-pixel.
The above described prior art permits half-tone representation, but disadvantageously flickers are caused by ON-OFF control of every pixel in a selected frame or frames. The lightness characteristics of the filters used in a color display panel are not taken into consideration, and therefore it is difficult to provide desired half-tone representation.